\documentclass[]{beamer}
% Class options include: notes, notesonly, handout, trans,
%                        hidesubsections, shadesubsections,
%                        inrow, blue, red, grey, brown

% Theme for beamer presentation.
\usepackage{beamerthemesplit} 
\usepackage{graphics} % for pdf, bitmapped graphics files
\usepackage{epstopdf}
\usepackage{graphicx}
\usepackage{subfigure}
\usepackage{stfloats}
\usepackage{fixltx2e}
\usepackage{wrapfig}
\usepackage{verbatim}
% Other themes include: beamerthemebars, beamerthemelined, 
%                       beamerthemetree, beamerthemetreebars  

\newcommand{\ie}[1] {
  \begin{itemize}
    #1
  \end{itemize}
}

\newcommand{\ee}[1] {
  \begin{enumerate}
    #1
  \end{enumerate}
}



\title{The PowerXCell 8i Processor Architecture}    % Enter your title between curly braces
\author{Edward Wertz, Arisoa Randrianasolo, Quan Gen}                 % Enter your name between curly braces
\institute{Texas Tech University}      % Enter your institute name between curly braces
\date{\today}                    % Enter the date or \today between curly braces

\begin{document}

%title page
\begin{frame}
\titlepage
\end{frame}


\section{The Cell Architecture}

\begin{frame}
\noindent {\bfseries The Cell Architecture}
\ie{
\item Main Processor - Power Processing Element (PPE)
\item Co-Processors - Synergistic Processing Elements (SPE)
\item Bus - Element Interconnect Bus (EIB)
\item Main Memory - Memory Interface Controller (MIC) and Rambus XDR RAM
\item IO Controllers - IOIF0, IOIF1
\ie{
\item Rambus FlexIO protocol
\item Broadband Interface protocol (extends EIB). 
}
}
\end{frame}


\begin{frame}
\begin{figure}[h]
  \begin{center}
    \includegraphics[height=.9\textheight]{cell_block.jpg}
  \end{center}
\end{figure}
\end{frame}


\begin{frame}
\begin{figure}
  \begin{center}
    \includegraphics[height=.9\textheight]{chip.jpg}
  \end{center}
\end{figure}
\end{frame}

\subsection{Power Processing Element}

\begin{frame}
\noindent {\bfseries Power Processing Element (PPE)}
\ie{
\item standard (RISC) 64-bit PowerPC processor
\item frequency 3.2 GHz 
\item PowerPC and Vector/SIMD Multimedia instruction sets
\item runs legacy 32-bit and 64-bit PowerPC programs
\item Programs
\ie{
\item Hosts the Operating system
\item Executes non-SPE portion of application programs
}
}
\end{frame}
\begin{frame}
\begin{figure}[h]
  \begin{center}
    \includegraphics[width=1\textwidth]{ppe_block.jpg}
  \end{center}
\end{figure}
\end{frame}

\begin{frame}
\noindent {\bfseries Power Processing Element (PPE) continued}
\ie{
\item 32 general registers
\item 32 128-bit SIMD vector/multimedia registers
\ie{\item  2  64-bit, 4 32-bit, 8 16-bit, and 128 1-bit operations}
\item 64 KBs of L1 cache
\ie{
\item 32 KB for instructions
\item 32 KB for data
}
\item 512 KB of level 2 cache
\item 2 thread execution by alternating threads
\item fetch 4 instructions/cycle per thread
\item issues up to 2 instructions per cycle, in order.
\item L2 and address translation caches are manually controlled to facilitate real time processing. 
\item 23 stage pipeline.
}
\end{frame}


\begin{frame}
\begin{figure}[h]
  \begin{center}
    \includegraphics[width=1\textwidth]{ppe_pipeline.jpg}
  \end{center}
\end{figure}
\end{frame}
 

\subsection{Synergistic Processing Element}

\begin{frame}
\noindent {\bfseries Synergistic Processing Element (SPE)}
\ie{
\item 6-8 SPEs in a Cell Processor
\item RISC Processor 
\item frequency 3.2 GHz 
\item IO handled by Memory Flow Controller (MFC)
\item Computations handled by Synergistic Processing Unit (SPU). 
}
\end{frame}


\begin{frame}
\begin{figure}[h]
  \begin{center}
    \includegraphics[width=1\textwidth]{spe_block.jpg}
  \end{center}
\end{figure}
\end{frame}

\begin{frame}
\noindent {\bfseries IO: Memory Flow Controller (MFC)}
\ie{
\item 32-bit Interrupts to PPE
\item 32-bit mailbox, polled by PPE
\item Direct Memory Access (DMA) through EIB
\ie{
\item 128 Bytes/cycle bandwidth
\item upto 16KB data transfers in one DMA request
\item upto 16 outstanding DMA requests. 
\item SPE to/from Main Memory
\item SPE to/from another SPE
\item SPE to/from PPE
}
}
\end{frame}

\begin{frame}
\noindent {\bfseries Synergistic Processing Unit (SPU)}
\ie{
\item No Cache
\item 256 KB of local store memory (LS) for instructions and data
\ie{
\item 128 Byte/cycle data transfer from/to MFC
\item 16 Bytes/cycle data transfer from/to SPE.
\item Instructions fetched in 32 4B groups. aligned to 64B boundaries
}
\item 128 128-bit SIMD registers
\ie{
\item 2 64-bit, 4 32-bit, 8 16-bit, 16 8-bit, or 128 1-bit operations
\item Progammer/Compiler tuned code for real time execution. 
\item Loop unrolling to keep pipeline filled
\item 6 read ports and 2 write ports
}
\item Issues up to 2 in-order instructions, one per execution pipeline.
}
\end{frame}

\begin{frame}
\begin{figure}[h]
  \begin{center}
    \includegraphics[width=1\textwidth]{spe_pipeline.jpg}
  \end{center}
\end{figure}
\end{frame}


\subsection{Element Interconnect Bus}

\begin{frame}
\noindent {\bfseries Element Interconnect Bus (EIB)}
\ie{
\item Bus frequency is half clock frequency (1.6 GHz)
\item 4 unidirectional rings
\ie{
\item 2 clockwise 
\item 2 counterclockwise
}
\item 16 bytes per ring per bus clock tick, 8 per cpu clock tick
\item The Arbiter coordinates traffic on bus. 
\item Arbiter can initiate 1 data transfer per bus clock tick 
\item upto 128Bytes per data transfer.
\item upto 3 simultaneous transfers per ring. 
\item upto 204 GB/s bandwidth through EIB.  
\item The ring topology was chosen over a cross-bar to save space on the die. 
}
\end{frame}

\begin{frame}
\begin{figure}[h]
  \begin{center}
    \includegraphics[width=1\textwidth]{eib_topology.jpg}
  \end{center}
\end{figure}
\end{frame}

\begin{frame}
\begin{figure}[h]
  \begin{center}
    \includegraphics[height=.9\textheight]{eib_8example.jpg}
  \end{center}
\end{figure}
\end{frame}



\subsection{Memory Interface Controller and Rambus XDR Memory}

\begin{frame}
\noindent {\bfseries Memory Interface Controller (MIC)}
\ie{
\item Two memory channels, each connecting to up to 8 memory modules.  
\item 512 MB of Rambus XDR ram possible 
\item Per Channel
\ie{
\item 3.2 GHz frequency
\item 32-bit wide
\item up to 12.8 GB/s bandwidth. 
}
\item up to 25.6 GB/s bandwidth total. 
}
\end{frame}

\subsection{Networking with FlexIO and The Broadband Interface }

\begin{frame}
{\bfseries Networking Modules}
\ie{
\item IOIF\_1
\ie{
\item Implements the Rambus FlexIO protocol
\ie{
\item incoherent capable
\item outbound 6 Bytes/cycle = 30 GB/s. 
\item inbound 5 Bytes/cycle = 25 GB/s.
}
}
\item IOIF\_0
\ie{
\item Implements the Rambus FlexIO protocol
\ie{
\item incoherent capable
\item outbound 6 Bytes/cycle = 30 GB/s. 
\item inbound 5 Bytes/cycle = 25 GB/s.
}
\item Broadband Interface Protocol (BIF)
\ie{
\item coherent protocol for extending the EIB to other devices
\item outbound 4 Bytes/cycle = 20 GB/s
\item inbound 4 Bytes/cycle = 20 GB/s 
}
}
}
\end{frame}

\begin{frame}
\begin{figure}
  \begin{center}
    \includegraphics[height=0.4\textheight]{single_cell.jpg}
  \end{center}
\end{figure}
\begin{figure}
  \begin{center}
    \includegraphics[height=0.4\textheight]{cell_paired.jpg}
  \end{center}
\end{figure}
\begin{wrapfigure}{R}{0.7\textwidth}
  \begin{center}
    \includegraphics[width=0.7\textwidth]{cell_quad.jpg}
  \end{center}
\end{wrapfigure}
\end{frame}

\begin{comment}

The two IO modules, called IOIF1 and IOIF0, support the Rambus FlexIO interface.  The IOIF0 module further provides what is called the Broadband Interface Protocol which is a coherent connection seemlessly extending the Element Interconnect Bus to another device, usually another Cell processor.  The IOIF0/BIF module is capable of up to 6 Bytes outbound and 5 Bytes inbound per cycle or 30GB/s out and 25GB/S in, scalable at 5GB/s increments. The IOIF1 module scales from 0 to 2 Bytes in either direction, upto 10GB/s in or out.  The BIF coherent connection uses 4 outgoing and 4 incoming channels to extend the EIB.  The network protocol is layered into four abstractions, the physical layer, the data link layer (packet transmission), the transport layer (packet generation and parsing), and the logical layer at the highest level, compatible with the EIB\cite{CBEIMI}.  

The Cell processor has three primary configurations.  The standalone processor in Figure~\ref{fig:9} uses the IOIF or FlexIO protocol with both IO modules.  Figure~\ref{fig:10} depicts two Cell processors directly connected to each other through the BIF protocol on IOIF0, leaving IOIF1 exposed for IO to the external network.  The max configurations for clustering Cells is 4 cells networked through a switch connecting the 4 EIB rings via the BIF protocol.  This configuration is designed for blades of a high performance computing cluster. In this scenario IOIF1 is used to connect to shared memory, more blades and other devices\cite{Kah}\cite{CBEIMI}.

\end{comment}
\end{document}